Transistor Switch Visualization | MOSFET, BJT, CMOS NOT and NAND

The idea: a switch you work with a voltage

A light switch connects two wires when you press it. A transistor does the same, but it is worked by a voltage instead of a finger: the voltage on one terminal decides whether current can flow between the other two. Because the output of one transistor can drive the input of the next, switches can control switches, and that is all a digital computer is.

Four panels: an nMOS with 0 V on its gate equals an open switch, with 5 V a closed switch; a pMOS with 0 V on its gate equals a closed switch, with 5 V an open switch. — An nMOS closes when its gate is high; a pMOS (the small circle on its gate) closes when its gate is low.

The page draws wires at 2.5 V or more in dark blue and lower wires in grey. A conducting channel is green, a half-on one orange, an open one white. Pick a circuit and an input voltage A (and B for the NAND), or press Truth Table to try every input, one row per step. The supply is V_DD = 5 V; 0 V means logic 0 and 5 V logic 1.

The nMOS transistor: gate, threshold, channel

A MOSFET (metal-oxide-semiconductor field-effect transistor) has a gate, a source and a drain. The gate sits on a thin layer of glass (silicon dioxide), so no current flows into it. In an nMOS, a positive gate voltage pulls electrons to the surface under the gate. Once the gate is more than the threshold voltage V_th (1 V here) above the source, those electrons form a channel that connects source and drain.

In the nMOS switch a 1 kΩ lamp hangs from V_DD, and the transistor connects its lower end to ground. With 0 V or 0.8 V on the gate there is no channel: no current, the lamp is dark, and V_out stays at 5 V. With 5 V on the gate the channel acts like a resistor of about 50 Ω: 4.76 mA flows, the lamp lights and V_out drops to 0.24 V (Demo: nMOS switch, 5 V on the gate turns it on). A 1 in gives a 0 out, so this one transistor is already an inverter.

Fully on, half on, off

Between the two ends, the transistor is neither open nor closed. Just above V_th the channel is thin and caps the current at k/2 · (V_GS − V_th)², the saturation region (here k = 5 mA/V²). At 1.5 V on the gate only 0.76 mA gets through, so the lamp is dim and V_out = 4.24 V, still a 1. With a strong gate voltage the transistor is in the linear (triode) region and behaves like a small resistor (Demo: nMOS sweep, half on at 1.5 V).

Output voltage against input voltage from 0 to 5 V for three circuits: the CMOS NOT falls steeply around 2.5 V from 5 V to 0 V; the nMOS switch with a lamp falls after 1 V and ends at 0.24 V; the BJT switch falls between 0.7 V and 1.2 V and ends at 0.2 V. Bands mark logic 1 above 3.5 V and logic 0 below 1.5 V. — The transfer curve: digital circuits only use the flat ends, where a small change of the input does not change the output.

This is why logic uses only two voltage ranges. Here anything at or below 1.5 V counts as 0 and anything at or above 3.5 V as 1. A gate whose output lands in between (orange boxes on the canvas) would be read differently by different gates downstream.

The BJT: current in, current out

A bipolar junction transistor (BJT) has a base, a collector and an emitter. It is controlled by current, not voltage. The base-emitter junction is a diode, so nothing flows until the base is about V_BE = 0.7 V above the emitter. Then the base current I_B = (V_in − 0.7 V) / R_B lets through a collector current β · I_B, here with β = 100.

Cutoff (V_in below 0.7 V): no base current, no collector current. Switch open.
Active: at 0.8 V, I_B = 0.01 mA and I_C = 1 mA, so V_out = 4 V. The transistor amplifies; it is not a switch yet.
Saturation: at 5 V, I_B = 0.43 mA asks for 43 mA, but the lamp allows only 4.8 mA. The transistor is fully on with V_CE = 0.2 V. Switch closed (Demo: BJT, the base current decides).

	MOSFET	BJT
controlled by	gate voltage V_GS	base current I_B
turns on at	V_th, about 0.3–1 V	V_BE ≈ 0.7 V
input current when on	0 (insulated gate)	I_B flows all the time
"fully on" voltage drop	I · R_on, can be millivolts	V_CE(sat) ≈ 0.2 V
used for	almost every chip (CMOS), power switches	analog amplifiers, older logic (TTL), some power stages

pMOS and the CMOS inverter

The nMOS switch has a weakness: when it is on, current flows through the lamp (or a pull-up resistor) all the time. A pMOS transistor is the mirror image of an nMOS: it conducts when its gate is at least V_th below its source, so a pMOS with its source on V_DD is on when the input is 0. CMOS (complementary MOS) puts a pMOS between V_DD and the output and an nMOS between the output and ground, with both gates on the input.

A = 0 V: the pMOS is on, the nMOS off. Y is connected to V_DD: Y = 5 V = 1.
A = 5 V: the pMOS is off, the nMOS on. Y is connected to ground: Y = 0 V = 0.

In both cases one switch is open, so no current flows from V_DD to ground (Demo: CMOS NOT, one transistor on at a time). A CMOS gate uses power only while it switches. That is why a phone chip with billions of transistors does not melt. During the switch, for inputs between 1 V and 4 V, both transistors conduct at once: at 2.5 V a short-circuit current of 6.33 mA flows straight through (Demo: CMOS NOT sweep, both on in the middle). Real gates pass through this zone quickly.

The CMOS NAND: series and parallel

For two inputs, CMOS uses the rule: switches in series make AND, switches in parallel make OR. The NAND has two nMOS in series as the pull-down: Y is pulled to 0 only if A and B are both 1. It has two pMOS in parallel as the pull-up: Y is pulled to 1 if A or B is 0. The two networks are exact complements, so for every input exactly one of them conducts (Demo: CMOS NAND truth table).

A	B	pull-up (pMOS ∥)	pull-down (nMOS in series)	Y
0	0	both on	open	1
0	1	pMOS A on	open	1
1	0	pMOS B on	open	1
1	1	open	both on	0

The same rule swapped gives a NOR: nMOS in parallel, pMOS in series. CMOS gates naturally invert, so an AND gate is a NAND followed by a NOT: 6 transistors instead of 4.

From NAND to every gate

NAND is universal: every logic function can be built from NAND gates alone. Tie both inputs together and it is a NOT. Add a NOT after it and it is an AND. Invert both inputs first and De Morgan's law turns it into an OR.

Three gate diagrams: NOT made from one NAND with its inputs tied, AND made from a NAND followed by a NAND used as NOT, and OR made from two NANDs inverting A and B feeding a third NAND. — NOT, AND and OR from NAND gates alone, with the transistor count of each.

From here the next level up is gates as boxes: Combinational Logic builds half and full adders, a ripple-carry adder, multiplexers and a 4-bit ALU from these gates, with a delay for every gate. Each gate delay is the time the transistors need to charge or discharge the wire behind them. The whole stack from electrons to C code is in Levels of Abstraction in a Computer.

What the page leaves out

Time. Every circuit here is a DC operating point: it settles at once. Real gates drive the capacitance of the wires and gates behind them, and that charging time is the gate delay. The dynamic power C · V² · f spent on it is most of a chip's power.
A simple transistor model. The MOSFET uses the textbook square law with one k and one V_th for both types. Real pMOS are about twice as weak as nMOS, so they are drawn wider, and modern short-channel transistors follow other equations. The BJT uses a fixed β and V_BE.
Leakage. An "off" transistor still leaks a tiny current, and in modern chips with billions of transistors that leakage is a large share of the power.
Physics of the channel. Doping, the p-n junctions and the body terminal are not shown; the source of each nMOS is assumed tied to the substrate.
Memory. Feeding gates back into each other makes latches and flip-flops: see Sequential Logic. Transmission gates and inverters are enough to build memory: A Latch and a Flip-Flop Built from Transistors builds a 12-transistor D latch and a 20-transistor flip-flop.